The integration of carbon nanostructures as channel materials in the next generation of electronic devices offers many advantages over the continued scaling of silicon (Si). Carbon nanostructures such as carbon nanotubes are a nanoscale form of carbon that exhibits extremely high current carrying capacity and mobilities, which are several orders of magnitude beyond the theoretical limit for Si. Furthermore, carbon nanotubes are low-dimensional (ultra-thin-body) materials, which allows them to be aggressively scaled in FETs (field-effect transistors) without incurring deleterious short-channel effects that hinder modern scaled devices.
For carbon nanotube field-effect transistors (CNTFETs) to be technologically relevant for highly integrated digital applications, it is important to realize a robust self-aligned device structure. Conventional self-aligned transistors, such as all current CMOS technology devices, make use of a pre-formed gate region as a mask for implanting source and drain contacts. Because the gate acts as an implant mask, the source and drain are formed in direct and consistent proximity to the gate, thus, self-aligned. A self-aligned device is critical because it ensures uniformity of key parameters such as parasitic capacitance, thus enabling uniform operation of the transistors across a chip. However, these conventional techniques are not applicable for nanotube field-effect transistors.